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ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 1 of 11 normally ? off silicon carbide junction transistor features package ? 175 c maximum operating t emperature ? gate oxide free sic s witch ? exceptional safe operating area ? excellent gain linearity ? temperature independent s witchi ng p erformance ? low output capacitance ? positive temperature coefficient of r ds,on ? suitable for connecting an anti - parallel d iode to - 247 advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short - circuit withstand capability ? lowest - in - class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? down hole oil drilling, geothermal instrumentation ? hybrid electric vehicles (hev) ? solar inverters ? switched - mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives table of contents section i: absolute maximum ratings ................................ ................................ ................................ .......... 1 section ii: static electrical characteristics ................................ ................................ ................................ ... 2 section iii: dynamic electrical characteristics ................................ ................................ ............................ 2 section iv: figures ................................ ................................ ................................ ................................ .......... 3 section v: driving the ga50jt17 - 247 ................................ ................................ ................................ ........... 7 section vi: package dimensions ................................ ................................ ................................ ................. 11 section vii: spice model parameters ................................ ................................ ................................ ......... 1 2 section i: absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 17 00 v continuous drain current i d t c = 2 5c 100 a fig. 17 continuous drain current i d t c = 14 5c 5 0 a fig. 17 continuous gate current i g 3.5 a turn - off safe operating area rbsoa t vj = 17 5 o c, clamped inductive load i d,max = 5 0 @ v ds v dsmax a fig. 19 short circuit safe operating area scsoa t vj = 17 5 o c, i g = 1 a , v ds = 12 00 v, non repetitive > 20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 2 5 c / 145 c , t p > 100 ms 583 / 116 w fig. 16 storage temperature t stg - 55 to 175 c s g d d v ds = 17 00 v r ds(on) = 2 0 m i d ( tc = 25 c) = 100 a i d (tc > 1 25c ) = 50 a h fe ( tc = 25c ) = 100
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 2 of 11 section ii: static electrical characteristics a: on state b: off state c: thermal section iii: dynamic electrical characteristics a: capacitance and gate charge b: switching 1 1 ? all times are relative to the drain - source voltage v ds parameter symbol conditions value unit notes min. typical max. drain ? source on r esistance r ds(on) i d = 5 0 a, t j = 25 c i d = 5 0 a, t j = 1 5 0 c i d = 5 0 a, t j = 175 c 20 36 4 2 m fig. 4 gate ? source saturation voltage v gs,sat i d = 50 a, i d /i g = 40 , t j = 25 c i d = 50 a, i d /i g = 30 , t j = 175 c 3.42 3.23 v fig. 7 dc current gain h fe v ds = 8 v, i d = 5 0 a , t j = 25 c v ds = 8 v, i d = 5 0 a , t j = 12 5 c v ds = 8 v, i d = 5 0 a , t j = 17 5 c 100 65 58 ? fig. 5 drain leakage current i dss v ds = 17 00 v, v gs = 0 v, t j = 25 c v ds = 17 00 v, v gs = 0 v, t j = 1 5 0 c v ds = 17 00 v, v gs = 0 v, t j = 17 5 c 0.5 1 3 a fig. 8 gate leakage current i s g v sg = 2 0 v, t j = 25 c 20 na thermal resistance, junction - case r thjc 0. 26 c/w fig. 20 parameter symbol conditions value unit notes min. typical max. input capacitance c is s v gs = 0 v, v d s = 12 00 v, f = 1 mhz 720 5 pf fig. 9 reverse transfer/output capacitance c rss /c oss v d s = 12 00 v, f = 1 mhz 12 0 pf fig. 9 output capacitance stored energy e oss v gs = 0 v, v d s = 12 00 v, f = 1 mhz 100 j fig. 10 effective output capacitance, time related c os s ,tr i d = constant, v gs = 0 v, v ds = 0?12 00 v 194 pf effective output capacitance, energy related c os s ,er v gs = 0 v, v ds = 0?12 00 v 139 pf gate - source charge q gs v gs = - 5?3 v 55 nc gate - drain charge q gd v gs = 0 v, v ds = 0?12 00 v 233 nc gate charge - total q g 2 88 nc internal gate resistance ? zero bias r g(int - zero ) f = 1 mhz, v ac = 50 mv, v ds = 0 v, v gs = 0 v, t j = 17 5 oc 0.59 internal gate resistance ? on r g(int - on) v gs > 2 . 5 v , v ds = 0 v, t j = 17 5 oc 0.09 turn o n delay time t d(o n ) t j = 25 oc, v ds = 12 00 v, i d = 5 0 a, inductive load refer to section v for additional driving information. 17 ns fall time , v ds t f 47 ns fig. 11 , 13 turn o ff delay time t d(o ff ) 39 ns rise time , v ds t r 25 ns fig. 12 , 14 turn o n delay time t d(o n ) t j = 17 5 oc, v ds = 12 00 v, i d = 5 0 a, inductive load 17 ns fall time , v ds t f 47 ns fig. 11 turn o ff delay time t d(o ff ) 44 ns rise time , v ds t r 2 3 ns fig. 12 turn - on energy per pulse e on t j = 25 oc, v ds = 12 00 v, i d = 5 0 a, inductive load refer to section v . 1830 j fig. 11 , 13 turn - off energy per pulse e off 62 8 j fig. 12 , 14 total switching energy e t ot 245 8 j turn - on energy per pulse e on t j = 17 5 oc, v ds = 12 00 v, i d = 5 0 a, inductive load 180 0 j fig. 11 turn - off energy per pulse e off 57 7 j fig. 12 total switching energy e t ot 2377 j
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 3 of 11 section iv: figures a: static characteristic s figure 1: typical output characteristics at 25 c figure 2 : typi cal output characteristics at 1 50 c figure 3 : typical output characteristics at 175 c figure 4: on - resistance vs. gate current fig ure 5 : dc current gain and normalized on - resistance vs. temperature figure 6: dc current gain vs. drain current
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 4 of 11 figure 7: typical gate ? source saturation voltage figure 8: typical blocking characteristics b: dynamic characteristic s figure 9: input, output, and reverse transfer capacitance figure 10: energy stored in output capacitance figure 11 : typical switching times and turn on energy losses vs. temperature figure 12 : typical switching times and turn o ff energy losses vs. temperature
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 5 of 11 figure 13 : typical switching times and turn on energy losses vs. drain current figure 14 : typical switching times and turn o ff energy losses vs. drain current c: current and power derating figure 15 : typical hard switched device power loss vs. switching frequency 2 figure 16: power derating curve figure 17 : drain current derating vs. temperature figure 18: forward bias safe operating area at t c = 25 o c 2 ? representative values based on device conduction and switching loss. actual losses will depend on gate drive conditions, device load, and circuit topology.
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 6 of 11 figure 19 : turn - off safe operating area figure 20 : transient thermal impedance figure 21 : drain current derating vs. pulse width
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 7 of 11 section v: driving the ga50jt17 - 247 drive topology gate drive power consumption switching frequency application emphasis availability ttl logic high low wide temperature range coming soon constant current medium medium wide temperature range coming soon high speed ? boost capacitor medium high fast switching production high speed ? boost inductor low high ultra fast switching coming soon proportional lowest high wide drain current range coming soon pulsed power medium n/a pulse power coming soon a: static ttl logic driving the ga 50jt17 - 247 may be driven using direct (5 v) ttl logic after current amplification. the (amplified) current level of the supply must meet or exceed the steady state gate current (i g,steady ) required to operate the ga 50jt1 7 - 247 . the power level of the supply can be es timated from the target duty cycle of the particular application. i g,steady is dependent on the anticipated drain current id through the sjt and the dc current gain h fe , it may be calculated from the following equation. an accurate value of the h fe may be read from figure 6 . ? ? , ?????? ? ? ? ?? ( ? , ? ? ) ? 1 . 5 figure 22: ttl gate drive schematic b: high speed driv ing the sjt is a current controlled transistor which requires a positive gate current for turn - on as well as to remain in on - state. an ideal gate current waveform for ultra - fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 23 which features a positive current peak during turn - on, a negative current peak during turn - off, and continuous gate current to remain on. figure 23: an idealized g a te c urrent w aveform for fast switching of an sjt. an sjt is rapidly switched from its blocking state to on - state, when the necessary gate charge, q g , for turn - on is supplied by a burst of high gate current, i g, on , until the gate - source capacitance, c gs , a nd gate- drain capacitance, c gd , are fully charged. ? ?? = ? ? , ?? ? ? 1 ? ?? ? ?? + ? ?? sic sjt d s g ttl gate signal 5 / 0 v ttl i/p i g,steady 5 v
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 8 of 11 ideally, i g,p on should terminate when the drain voltage falls to its on - state value in order to avoid unnecessary drive losses during the steady on- state. in practice, the rise time of the i g, on pulse is affected by the parasitic inductances, l par in the device package a nd drive circuit. a voltage developed across the parasitic inductance in the source path, l s , can de - bias the gate - source junction, when high drain currents begin to flow through the device. the voltage applied to the gate pin should be maintained high eno ugh, above the v gs, sat ( see figure 7 ) level to counter these effects. a high negative peak current, - i g, off is recommended at the start of the turn - of f transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn - off. while satisfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn - off transition. two high - speed drive topologies for the sic sjts are presented below. b:1: high speed, low loss drive with boost capacitor, ga03iddjt30 - fr4 the ga 50jt17 - 247 may be driven using a high speed, low loss drive with boost capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn - on and turn - off and a continuous gate current w hile in on- state. a 3 kv isolated evaluation gate drive board ( ga03iddjt30 - fr4 ) utilizing this topology is commercially available for high and low - side driving, its datash eet provides additional details about this drive topology. figure 24: topology of the ga03iddjt30 - fr4 two voltage source gate driver. the ga03iddjt30 - fr4 evaluation board comes equipped with two on board gate drive resistors (rg1, rg2) pre - installed for an effective gate resistance 3 of r g = 3.75 ?. it may be necessary for the user to reduce rg1 and rg2 under high drain current conditions for safe operation of the ga 50jt17 - 247. the steady state current supplied to the gate pin of the ga 50jt17 - 247 with on - board r g = 3.75 ?, is shown in figure 25 . the maximum allowable safe value of r g for the user?s required drain current can be read from figure 26 . for the ga 50jt17 - 247, r g must be reduced for i d ~14 a for safe operation with the ga03iddjt30 - fr4 . for operation at i d ~1 4 a, r g may be calculated from the following equation, which contains the dc current gain h fe ( figure 6 ) and the gate- source saturation voltage v gs,sat ( figure 7 ) . ? ? , ??? = ? 4 . 7 ? ? ? ?? , ??? ? ? ? ?? ( ? , ? ? ) ? ? ? 1 . 5 ? 0 . 6 i g cg2 sic sjt gate signal v gh d1 r4 r1 u1 v gl v ee u2 v gl v ee v gl u3 v gh u4 v ee c2 c1 v ee u5 v gl v ee u6 cg1 rg1 rg2 r2 r3 c5 c3 c4 c8 c6 c9 c10 +12 v +12 v vcc high vcc high rtn vcc low vcc low rtn signal signal rtn gate source voltage isolation barrier ga03iddjt30-fr4 gate driver board d s g
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 9 of 11 figure 25 : typical steady state gate current supplied by the ga03iddjt30 - fr4 board for the ga50jt17 - 247 with the on board resistance of 3.75 ? figure 26 : maximum gate resistance for safe operation of the ga50jt17 - 247 at different drain currents using the ga03iddjt30 - fr4 board. b:2: high speed, low loss drive with boost inductor a high speed, low - loss driver with boost inductor is also capable of driving the ga 50jt17 - 247 at high - speed. it utilizes a gate drive inductor instead of a capacitor to provide the high - current gate current pulses i g,on and i g,off . during operation, inductor l is charged to a specified i g,on current value then made to discharge i l into the sjt gate pin using logic control of s 1 , s 2 , s 3 , and s 4 , as shown in figure 27 . after turn on, while the device remains on the necessary steady state gate current i g,stea dy is supplied from source v cc through r g . please refer to the article ?a current - source concept for fast and efficient driving of silicon carbide transistors by dr. jacek r?bkowski for additional informati on on this driving topology. 4 figure 27 : simplified inductive pulsed drive topology 3 ? r g = (1/ rg1 +1/rg2) -1 . driver is pre - installed with rg1 = rg2 = 7.5 ? 4 ? archives of electrical engineering. volume 62, issue 2, pages 333 ? 343, issn (print) 0004 - 0746, doi: 10.2478/aee - 2013 - 0026 , june 2013 sic sjt d s g l r g v ee v cc v cc v ee s 1 s 2 s 3 s 4
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 10 of 11 c: proportional gate current driving for applications in which the ga 50jt17 - 247 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. a proportional gate driver relies on insta ntaneous drain curr ent i d feedback to vary the steady state gate current i g,steady supplied to the ga 50jt17 - 247 c:1: voltage controlled proportional driver the voltage controlled proportional driver relies on a gate drive ic to detect the ga 50jt17 - 247 drain - source voltage v ds du ring on - state to sense i d . the gate drive ic will then increase or decrease i g,steady in response to i d . this allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d high er. a high voltage diode connected between the drain and sense protects the ic from high - voltage when the driver and ga 50jt17 - 247 are in off - state. a simplified version of this topology is shown in figure 29 , additional information will be available in the future at http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ figure 28 : simplified voltage controlled proportional driver c:2: current controlled proportional driver the current controlled proportional driver relies on a low - loss transformer in the drain or source path to provide feedback i d of t he ga 50jt17 - 247 during on - state to supply i g,steady into the device gate. i g,steady will then increase or decrease in response to i d at a fixed forced current gain which is set be the turns ratio of the transformer, h force = i d / i g = n 2 / n 1 . ga 50jt 17- 247 is initially tuned - on using a gate current pulse supplied into an rc drive circuit to allow i d current to begin flowing. this topology allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d higher. a simplified version of this topology is shown in figure 29, additional information will be available in the future at http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/. figure 29 : simplified current controlled proportional driver sic sjt proportional gate current driver d s g gate signal i g,steady hv diode sense signal output sic sjt d s g n 2 n 2 n 1 n 3 gate signal
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 11 of 11 section vi: package dimensions to - 247 package outline note 1. controlled dimension is inch. dimension in bracket is millimeter. 2. dimensions do not include end flash, mold flash, material protrusions revision history date revision comments supersedes 2015/01/29 4 updated electrical characteristics 2014/12/18 3 updated electrical characteristics 2014/11/12 2 updated electrical characteristics 2014/08/20 1 updated electrical characteristics 2014/06/20 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specifications and data in this document without no tice . genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or implied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life - saving, medical, aircraft n avigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in deat h, personal injury and/or property damage. (15.748) (16.256) 0.620 0.640 ? 0.140 (3.556) 0.143 (3.632) 0.065 (1.651) 0.083 (2.108) 0.040 (1.016) 0.055 (1.397) 0.2146 (5.451) bsc. 0.016 (0.406) 0.031 (0.787) 0.059 (1.498) 0.098 (2.489) 0.171 (4 .699) 0.208 (5 .283) 0.075 (1.905) 0.115 (2.921) (4.318 ref.) 0.170 ref. (5.486) 0.216 0.819 0.844 (20.803) (21.438) 0.780 0.800 (19.812) (20.320) 0.177 max (4.496) 0.242 bsc. (6.147 bsc.) ? 0.118 (3.00) 0.22 (5.59) ? 0.283 (7.19) 0.652 (16.56) 0.55 (13.97) 0.236 (5.99) 0.054 (1.36) 0.012 (0.3) 0.045 (1.14) ga50jt17-247 xxxxxx lot code
ga50jt17 - 247 jan 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ pg 1 of 1 section vii: spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website ( http://www.genesicsemi.com/images/products_sic/sjt/ga50jt17- 247_spice.pdf ) into ltspice (version 4) software for simulation of the ga50jt17 -2 47. * model of genesic semiconductor inc. * * $revision: 2 . 2 $ * $date: 29- jan- 2015 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2015 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * .model ga50jt17 npn + is 9.833e- 48 + ise 1.073e- 26 + eg 3.23 + bf 110 + br 0.55 + ikf 9000 + nf 1 + ne 2 + rb 0.95 + irb 0.005 + rbm 0.073 + re 0.005 + rc 0.014 + cjc 2.398e- 9 + vjc 2.8346 + mjc 0.4846 + cje 6.026e- 09 + vje 3.1791 + mje 0.5295 + xti 3 + xtb - 1.5 + trc1 9.00e- 3 + vceo 1700 + icrating 50 + mfg genesic_semiconductor * * end of ga5 0 jt17 spice model

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